1. Field of the Invention
The present invention relates to a clock signal reproducing apparatus for reproducing a clock signal which is synchronized with a bit stream signal used for the reproduction.
2. Description of the Prior Art
For example, in a demodulator used for a satellite communication, a transmission signal is received and demodulated to obtain a demodulated data signal which is a bit stream signal, and then a clock signal which is synchronized with the demodulated data signal is first reproduced from the demodulated data signal. Thereafter, a write-in operation of the demodulated data signal into a memory and a code error correction processing for the demodulated data signal are carried out by using the clock signal thus reproduced.
FIG. 6 is a timing chart showing an example of the demodulated data signal.
The demodulation data signal has a still more gentle waveform as compared with the waveform of a bit stream signal before transmission as shown in FIG. 6, because the frequency band of a transmission channel is limited, and the clock signal is reproduced from such a demodulated data signal. In the bit stream signal before transmission, the low level represents that the bit value is equal to zero, and the high level represents that the bit value is equal to 1. Accordingly, the bit stream signal shown in FIG. 6 has the bit value which is alternately changed between xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d.
Various methods for reproducing a clock signal have been hitherto proposed. A method of sampling and digitizing a demodulated data signal with an analog-to-digital converter while adjusting a sampling timing with a PLL (Phase Lock Loop) to obtain a clock signal has been most widely used.
FIG. 4 is a block diagram showing a clock signal reproducing apparatus based on a conventional system, and FIG. 5 is a timing chart showing the operation of the clock signal reproducing apparatus shown in FIG. 4.
In FIG. 4, oscillator 102 (VCXO) generates clock signal 104 whose frequency is varied in accordance with a control voltage, and supplies the clock signal as a sampling clock to analog-to-digital converter 106. The frequency of clock signal 104 generated by oscillator 102 is about twice as high as the bit rate of the demodulated signal inputted through input terminal 110. Analog-to-digital converter 106 samples demodulated data signal 110 from input terminal 110 at the rise-up time of the clock signal supplied from oscillator 102 to convert demodulated data signal 110 to a digital signal.
The normal demodulated data signal has a bit-value variation different from the signal of FIG. 6 in which the bit value is alternately changed between xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, and the arrangement of the bit values of the normal demodulated data signal is varied in accordance with the data content. Accordingly, FIG. 5 shows demodulated data signal 110 in order to explain the variation of the bit-value arrangement.
Data variation direction detector 112 outputs a logic signal representing the variation direction of demodulated data signal 110 on the basis of the most significant bit (MSB) of the output signal of analog-to-digital converter 106. Particularly, in FIG. 5, data variation direction detector 112 checks the output signal of analog-to-digital converter 106 at every other rise-up timing A of clock signal 104. When demodulated data signal 110 becomes higher during the period of one bit of the demodulated data signal (or during the period of two waves of clock signal 104), for example, the variation direction detection signal of the logic xe2x80x9c0xe2x80x9d is outputted from data variation direction detector 112. On the other hand, when demodulated data signal 110 becomes lower during the period of one bit of demodulated data signal 110, for example, the variation direction detection signal of the logic xe2x80x9c1xe2x80x9d is outputted from data variation direction detector 112.
Phase error detector 114 outputs a signal representing the amount of the phase error between demodulated data signal 110 and clock signal 104 on the basis of the output signal of analog-to-digital converter 106 at the timing B (the rise-up timing at the middle between timing A and timing Axe2x80x2) as shown in FIG. 5.
Particularly, multiplier 116 (XOR) comprises an exclusive OR circuit, and it exclusively ORs the output signal of data variation direction detector 112 and the output signal of phase error detector 114 and outputs the signal representing the exclusive OR result. Digital-to-analog converter 118 converts the output signal of multiplier 116 to an analog signal, and low-pass filter 120 (LPF) allows only low-frequency band components to pass therethrough and supplies the components as a control voltage to oscillator 102.
Accordingly, when there is a phase difference between demodulated data signal 110 and clock signal 104, oscillator 102 is supplied with the control voltage to vary the frequency of clock signal 104 so that the frequency of clock signal 104 is increased/decreased in accordance with the variation direction signal outputted from the data variation direction detection circuit. As a result, the phase difference between demodulated data signal 110 and clock signal 104 disappears, so that clock signal 105 whose frequency corresponds to the bit rate of demodulated signal 110 and whose phase is fixed with respect to that of demodulated data signal 110 is obtained from half-frequency divider 121 and outputted from output terminal 122 as a reproduced clock signal.
As explained above, in the conventional clock reproducing system, the sampling must be carried out at the frequency which is twice as high as the bit rate of demodulated data signal 110 in analog-to-digital converter 106. Therefore, for example, when demodulated data signal 110 is high-speed data having a bit rate of 100 Mbps or more, the operation speed of analog-to-digital converter 106 must be set to twice of the bit rate (i.e., the operation speed must be 200 MHz or more), and thus a very expensive analog-to-digital converter having a large power consumption must be used. Further, likewise, an oscillator which can oscillate at 200 MHz or more must be used as oscillator 102. Therefore, as in the case of analog-to-digital converter 106, very expensive oscillator having a large power consumption power must be used.
Therefore, when the demodulated data signal is of high-speed data having a bit rate of 100 Mbps or more, it is actually difficult to implement a practical clock signal reproducing apparatus by the conventional system.
In order to overcome the aforementioned disadvantages, the present invention has been made and accordingly has an object to provide a clock signal reproducing device in which both of the operation speed of a needed analog-to-digital converter and the oscillation frequency of a needed oscillator can be decreased to a half of the prior art.
According to an aspect of the present invention, there is provided a clock signal reproducing apparatus for reproducing a clock signal from a received bit stream signal, which comprises: an oscillator for generating the clock signal having a frequency which is substantially the same as the bit rate of the bit stream signal and varies in accordance with a control voltage applied thereto; a signal variation direction detection circuit for detecting whether an amplitude of the bit stream signal is increased or decreased during one period of the clock signal and outputting a variation direction signal representing a result of the detection; an analog-to-digital converter for converting the bit stream signal to a digital signal in synchronism with the clock signal; and an oscillator control circuit for supplying said oscillator with the control voltage corresponding to a value of the digital signal and a value of the variation direction signal, wherein whether to ascend or descend the control voltage according to an increase in the value of the digital signal is determined by the oscillator control circuit on the basis of the value of the variation direction signal.
In the clock signal reproducing apparatus according to the present invention, the oscillator operates at the frequency substantially equal to the bit rate of the bit stream signal, and generates the clock signal whose frequency is varied in accordance with the control voltage supplied thereto. In synchronism with the clock signal, the signal variation direction detection circuit outputs a variation direction signal representing whether the amplitude of the bit stream signal is increased or decreased during one period of the clock signal generated by the oscillator.
The analog-to-digital converter samples the bit stream signal in synchronism with the clock signal, and converts the bit stream signal to the digital signal. The oscillator control circuit supplies the control voltage corresponding to the amplitude of the digital signal output from the analog-to-digital converter to the oscillator, and the operation of ascending the control voltage as the amplitude of the digital signal increases and the operation of reducing the control voltage as the amplitude of the digital signal increases are switched to each other on the basis of the variation direction signal outputted from the signal variation direction detection circuit.
As a result, the frequency of the clock signal generated by the oscillator is the frequency equal to the bit rate of the bit stream signal at all times, and the phase thereof is fixed to the bit stream signal.
In the clock signal reproducing apparatus, it is not required that the variation direction of the bit stream signal is detected on the basis of the digital signal output from the analog-to-digital converter as in the case of the prior art, and thus the analog-to-digital converter may be operated at a half of the frequency of the prior art. Accordingly, what is required for the oscillator is to generate the clock signal having a half of the frequency of the prior art.